Thursday, October 16, 2008

Thomson Decoder Diagram

A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator, an error polynomial is generated based upon the syndrome in an error polynomial generator, an error location is determined from the error polynomial in the error location generator, an error magnitude is calculated from the error polynomial in the error magnitude generator and the codeword is corrected by a error corrected codeword generator responsive to location and error magnitude. An intra-decoder block messaging scheme is described in which one or more components generate inactivity messages to signal an ability to process data corresponding to a next codeword. A dual Chien search block implementation is described in which Chien block is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block. An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block implemented with a LIFO register.

This patent application is related to simultaneously filed U.S. patent application Ser. No. 10/055,076, filed Jan. 23, 2002 entitled DUAL CHIEN SEARCH BLOCKS IN AN ERROR-CORRECTING DECODER; and U.S. patent application Ser. No. 10/055,470, filed Jan. 23, 2002 entitled CHIEN SEARCH CELL FOR AN ERROR-CORRECTING DECODER, both of which are incorporated herein by reference in their entireties.